1. Field of the Invention
The present invention relates to a data driver for a plasma display panel (PDP), a driving method for a PDP, and a plasma display device using them, and a control method for the plasma display device.
2. Description of the Related Art
A plasma display panel (hereinafter, simply referred to as PDP) has many features. In general, the PDP is thin and flicker-free, has a large display contrast ratio and a high response speed, and can be relatively easily manufactured to have a large screen, for example. Moreover, the PDP is self-luminous and can emit multiple colors of light in accordance with selection of fluorescent materials.
Owing to these features, the PDP has been widely used in the arts of computer-related displays, home-use thin TV receivers, and the like in recent years.
PDPs are classified into an alternating-current (AC) discharge type and a direct-current (DC) discharge type according to an operating method. In the AC discharge type, electrodes are covered with a dielectric material and are indirectly operated in a state where AC discharge occurs. In the DC discharge type, electrodes are exposed to a discharge space and are operated in a state where DC discharge occurs.
The AC discharge type is further classified into a memory operation type and a refresh operation type in accordance with a driving method. The memory operation type uses a memory function of a discharge cell, whereas the refresh operation type does not use the memory function.
In the refresh operation type, the brightness is lowered with increase of the display capacity. Thus, the refresh operation type is typically used in a small PDP having a small display capacity. A PDP used in a thin TV receiver in recent years is usually the AC discharge memory operation type.
FIG. 1 is a cross-sectional view showing the structure of a display cell in a typical AC discharge memory operation type PDP.
As shown in FIG. 1, each display cell of the AC discharge memory operation type PDP generally includes a rear insulating substrate 1 made of glass; a front insulating substrate 2 made of glass; a transparent scanning electrode 3 formed on the front insulating substrate 2; a transparent sustain electrode 4 that is also formed on the front insulating substrate 2; a trace electrode 5 arranged to overlap the scanning electrode 3; a trace electrode 6 arranged to overlap the sustain electrode 4; a data electrode 7 formed on the rear insulating substrate 1 to perpendicularly intersect with the scanning electrode 3 and the sustain electrode 4; a discharge gas space 8 filled with a discharge gas formed of a gas of helium (He), neon (Ne), xenon (Xe), or the like, or a mixed gas of them; barriers 9 for ensuring the discharge gas space 8 and sectioning the display cell; a fluorescent material 11 that converts ultra-violet rays generated by discharge of the discharge gas into visible light 10; a dielectric layer 12 covering the scanning electrode 3 and the sustain electrode 4; a protection layer 13 for protecting the dielectric layer 12 against discharge, formed of magnesium oxide (MgO) or the like; and a dielectric layer 14 covering the data electrode 7.
A discharge operation of a selected display cell is now described with reference to FIG. 1.
When a pulse voltage larger than a discharge threshold value is applied across the scanning electrode 3 and the data electrode 7 so as to start discharge, positive and negative electric charges are attracted to surfaces of the dielectric layers 12 and 14 in accordance with a polarity of the pulse voltage, and are accumulated. A wall voltage that is an equivalent internal voltage caused by the accumulation of electric charges has an opposite polarity to that of the pulse voltage. Thus, an effective voltage within the display cell is lowered with growth of discharge and therefore discharge cannot be held even if the applied pulse voltage is kept to a constant value. Finally, discharge stops.
Then, when a sustain pulse that is a pulse voltage having the same polarity as that of the wall voltage is applied across the scanning electrode 3 and the sustain electrode 4 that are adjacent to each other, the wall voltage is added as the effective voltage to the sustain pulse and a total voltage exceeds the discharge threshold value. Thus, even if the amplitude of the sustain pulse is small, discharge occurs. Therefore, it is possible to hold discharge by continuously applying the sustain pulse across the scanning electrode 3 and the sustain electrode 4.
The above function is a memory function of a discharge cell. The sustain discharge can be stopped by applying a low voltage pulse that has a wide pulse-width and can neutralize the wall voltage, a narrow erasing pulse that is a pulse with approximately the same voltage as the narrow pulse-width sustain pulse, or a gentle pulse in which transition occurs at a rate of several volts per microsecond to the scanning electrode 3 or the sustain electrode 4.
Next, a structure of a conventional PDP driving device is described with reference to FIG. 2. FIG. 2 is a block diagram of an example of the conventional PDP driving device.
A PDP 21 is provided with a group of sustain electrodes 42 and a group of scanning electrodes 53 on one surface. The sustain electrodes 42 and the scanning electrodes 53 are arranged to be parallel to each other. The PDP 21 is also provided with a group of data electrodes 32 on a surface opposed to the above surface. The data electrodes 32 are arranged to intersect with the sustain electrodes 42 and the scanning electrodes 53 perpendicularly. A display cell 22 is formed at each of intersections of the sustain electrodes and scanning electrodes and the data electrodes. A sustain electrode X is provided to correspond to each of the scanning electrodes Y1, Y2, Y3, . . . , and Yn (n is a given positive integer) near the corresponding scanning electrode. The sustain electrodes X are connected at their one ends in common with each other.
A plurality of kinds of driver circuits that are required for driving the display cell 22 and a control circuit for controlling those driver circuits in the conventional PDP driving device are now described.
A data driver 31 that supplies data to a group of data electrodes 32 for one line so as to drive those data electrodes is provided in order to cause address discharge of the display cell 22. Moreover, a sustain driver circuit 40 that makes the sustain electrode group 42 commonly perform sustain discharge and a scanning driver circuit 50 that makes the scanning electrode group 53 commonly perform sustain discharge are provided in order to cause sustain discharge in the display cell 22.
In addition, a scanning driver 55 that sequentially scans the scanning electrode group 53 including the scanning electrodes Y1 to Yn is provided in order to cause discharge for selection and writing during an address period. The scanning driver 55 also applies a sustain pulse to its own electric supply source, thereby causing sustain discharge.
A control circuit 61 controls all operations of the data driver 31, the sustain driver circuit 40, the scanning driver circuit 50, the scanning driver 55, and the PDP 21.
A main part of the control circuit 61 is formed by a display data controller 62 and a driving timing controller 63. The display data controller 62 has a function of re-ordering display data input from the outside into data for driving the PDP 21. The display data controller 62 also has a function of temporarily storing a sequence of the re-ordered display data and transferring that sequence to the data driver 31 as display data DATA in synchronization with sequential scanning by the scanning driver 55 during address discharge. The driving timing controller 63 converts various signals such as a dot clock that are input from the outside into internal control signals for driving the PDP 21, thereby controlling the respective drivers and driver circuits.
Next, a driving sequence in the conventional PDP driving device is described with reference to FIG. 3. FIG. 3 is a time chart showing a state in which a plurality of sub-fields are formed within one field in the conventional PDP driving device.
The sub-fields (hereinafter, simply referred to as SFs) are formed by dividing one field having duration of 16.7 ms, for example, to have different weights from each other. In the example of FIG. 3, the number of the sub-fields is set to 8. The driving sequence is defined by combining those sub-fields in an appropriate manner so as to present 256 gray-scales.
Each sub-field is formed by a scanning period and a sustain discharge period. During the scanning period, display data in accordance with the weight of that sub-field is written. During the sustain discharge period, the display data for which writing has been instructed is displayed. An image of one field is displayed by combining the respective sub-fields.
FIG. 4 shows a detailed operation in one sub-field having a certain weight. FIG. 4 shows a sustain electrode driving waveform Wx that is commonly applied to the sustain electrodes X, scanning electrode driving waveforms Wy1 to Wyn that are applied to the scanning electrodes Y1 to Yn, respectively, and data electrode driving waveforms Wdi (1=i=k) that are applied to the data electrodes D1 to Dk, respectively.
One period of the sub-field is formed by the scanning period and the sustain discharge period. The scanning period is formed by a preliminary discharge period and a writing discharge period. A desired picture can be displayed by repeating those periods. The preliminary discharge period is used, if necessary, and it can be omitted.
The preliminary discharge period is a period for generating active particles and wall charges in the discharge gas space in order to make stable writing discharge occur during the writing discharge period. The preliminary discharge period is formed by a preliminary discharge pulse for causing discharge in all display cells of the PDP at the same time and a preliminary discharge erasing pulse for erasing ones of the wall charges generated by application of the preliminary discharge pulse, which obstruct writing discharge and sustain discharge.
During the sustain discharge period, sustain discharge is caused by utilizing a memory operation so as to emit light, in order to achieve desired brightness in a display cell in which writing discharge has been performed during the writing discharge period.
During the preliminary discharge period, first, a preliminary discharge pulse Pp is applied to the sustain electrodes X so as to make discharge occur in all the display cells. Then, a preliminary discharge erasing pulse Ppe is applied to the scanning electrodes Y1 to Yn to make erasing discharge occur, so that the wall charges accumulated by the preliminary discharge pulse are erased.
During the following writing discharge period, a scanning pulse Pw is sequentially applied to the scanning electrodes Y1 to Yn line by line, and a data pulse Pd is selectively applied to the data electrodes Di (1=i=k) in accordance with picture display data. Thus, writing discharge is made to occur in a cell that is to perform display and wall charges are generated.
During the following sustain discharge period, sustain discharge is made to continuously occur only in the display cell in which writing discharge occurred by sustain pulses Pc and Ps. After final sustain discharge is caused by a final sustain pulse Pce, the wall charges that are formed are erased by a sustain discharge erasing pulse Pse, thereby stopping sustain discharge and completing a light-emitting operation for one screen.
The brightness of the PDP is in proportion to the number of discharges, i.e., the number of repetition of the pulse voltage in a unit time.
Next, an operation of an address driver circuit for causing address discharge in the conventional PDP is described in more detail.
In general, the data driver 31 shown in FIG. 2 is formed by a plurality of PDP data driver ICs each having several tens to several hundreds of display data output terminals.
The PDP data driver IC (hereinafter, simply referred to as data driver IC) has a function of outputting a data pulse to a PDP in accordance with display data. In general, the data driver IC has several tens to several hundreds of terminals for outputting a data pulse. The data pulse is binary, i.e., has a high level and a low level.
The data driver IC generally includes a shift register 101, a latch circuit 102, an output control circuit 103, and a highly tolerant buffer 104, as shown in FIG. 5.
The shift register 101 has a function of transferring and holding display data DATA 105 input from one or more display data input terminals by using a clock CLK 106. The latch circuit 102 is formed by a register and has a function of taking in the display data stored in the shift register 101 by a latch signal from a latch input terminal LE 107 and holding the display data. The display data taken in the latch circuit 102 is output from output terminals 108 as data pulses through the output control circuit 103 and the highly tolerant buffer 104.
In general, the output control circuit 103 includes a high-blank control terminal HBLK 109 to which a high blanking signal for setting all data pulse outputs of the data driver IC to a high level (hereinafter, called as a high-blank state) is input, and a low-blank control terminal LBLK 110 to which a low blanking signal for setting all the data pulse outputs to a low level (hereinafter, called as a low-blank state) is input. Please note that each data driver IC is provided with one high-blank control terminal HBLK 109 and one low-blank control terminal LBLK 110 only, because both of those control terminals are used for controlling all the data pulse outputs at the same time.
The output control circuit 103 and the highly tolerant buffer 104 in the data driver IC have structures shown in FIG. 6, for example.
The output control circuit 103 includes an array of buffers Ba1, Ba2, Ba3, . . . , Ba(n−2), Ba(n−1), and Ban, an array of gates Ga1, Ga2, Ga3, . . . , Ga(n−2), Ga(n−1), and Gan that are formed by NAND circuits, respectively, and an array of gates Gb1, Gb2, Gb3, . . . , Gb(n−2), Gb(n−1), and Gbn that are formed by NAND circuits, respectively, as shown in FIG. 6.
All the NAND gates forming the gates Ga1, Ga2, Ga3, . . . , Ga(n−2), Ga(n−1), and Gan are connected at one inputs to input data IDATA1, IDATA2, IDATA3, . . . , IDATA(n−2), IDATA(n−1), and IDATAn through the buffers Ba1, Ba2, Ba3, . . . , Ba(n−2), Ba(n−1), and Ban provided in the former stage, respectively, and are connected at the other inputs to the high-blank control terminal HBLK in parallel.
All the NAND gates forming the gates Gb1, Gb2, Gb3, . . . , Gb(n−2), Gb(n−1), and Gbn are connected at one inputs to outputs of the gates Ga1, Ga2, Ga3, . . . , Ga(n−2), Ga(n−1), and Gan provided in the former stage, respectively, and are connected at the other inputs to the low-blank control terminal LBLK in parallel.
The highly tolerant buffer 104 is formed by buffer circuits Bb1, . . . , and Bbn each of which is tolerant of a high voltage and is connected between a high voltage power source and ground. The buffer circuits Bb1, . . . , and Bbn are connected at inputs to the gates Gb1, Gb2, Gb3, Gb(n−2), Gb(n−1), and Gbn provided in the former stage, and are connected at outputs to output terminals OUT1, OUT2, OUT3, . . . , OUT(n−2), OUT(n−1), and OUTn, respectively.
In the circuit shown in FIG. 6, both the high-blank control terminal HBLK and the low-blank control terminal LBLK are low active. Thus, when those control terminals HBLK and LBLK are high, the display data IDATA1 to IDATAn input from the latch circuit provided in the former stage are output without change. When only the high-blank control terminal HBLK is set to be active (low), all outputs become high (i.e., the high-blank state) irrespective of the input data. When the low-blank control terminal LBLK is set to be active (low), all the outputs become low (i.e., the low-blank state) irrespective of the input data.
In the high-blank state, a voltage between the data electrode and the scanning electrode is lowered because the data electrode is placed at a high level (e.g., about 80V). Thus, opposed discharge between the data electrode and the scanning electrode is controlled to be stopped. In the low-blank state, application of the data pulse to the data electrodes is forcedly stopped.
Such a data driver IC is described in NEC Paper Machine: μPD16373, published by NEC Corporation, General-purpose device division, Sales and technical support group, March, 2001, p. 5, Truth table 3 (Driver) and so on, for example. This publication describes control for setting the output voltage of the data driver to a high level, a low level, or high impedance, whereas the present invention is intended to achieve control for setting the output voltage to a high level and a low level only.
FIG. 7 shows typical connection between the data driver IC and the PDP.
As shown in FIG. 7, the PDP 21 includes data electrodes for each of cells displaying red, cells displaying green, and cells displaying blue (hereinafter, red, green, and blue are referred to as R, G, and B, respectively) and are arranged in the order of the R cells, the G cells, and the B cells. Output terminals of the data driver IC are connected to the thus arranged data electrodes, respectively.
In the PDP 21, a cell that is to perform display is selected by applying a data pulse to the data electrode in the aforementioned manner during the address period. In the selection of the cell, the control circuit 61 inputs the display data DATA, the clock CLK, the latch signal, the high blanking signal, the low blanking signal and the like to corresponding input terminals of each data driver IC, so that the data driver 31 outputs the data pulse to the PDP 21.
A PDP is formed by R, G, and B cells. In each cell, a fluorescent material of any one of R, G, and B is applied. The R, G, and B fluorescent materials have different properties and therefore voltage characteristics of a cell may be different between R, G, and B.
When a difference of the voltage characteristics between the colors is large, improper lighting occurs while a display is performed, thus degrading the display quality. Moreover, a required panel driving voltage becomes larger. Therefore, a withstand voltage of a device in a driving circuit has to be made higher, thus increasing a product cost.
On the other hand, a component in the PDP that can drive cells of each color independently of cells of other colors is the data electrode. Thus, in order to compensate for the voltage characteristics of the respective colors, a driving method is conceivable in which a driving pulse is applied to data electrodes for each of R, G, and B independently of other colors during the respective period other than the writing period.
In this method, in the case where the PDP 21 and the data driver 31 are connected to each other in a manner shown in FIG. 7, it is necessary to input the display data to the data driver and control on and off of pulse outputs of output terminals for each color, in order to independently apply the driving pulse to the cells of each of R, G, and B.
However, it takes several microseconds to transfer the display data to the shift register of the data driver IC forming the data driver. Thus, there is a limitation that independent control for each of R, G, and B requires the above data transfer time when the pulse is switched.
As shown in FIG. 8, an independent and separate data driver may be provided for every color in order to avoid the aforementioned problem. A typical data driver IC has a function of forcedly setting all its output terminals to a high level or a low level, as described above. Thus, with this function, it is possible to apply a driving pulse to data electrodes without data transfer. In this case, control cannot be independently performed for each color in the connection shown in FIG. 7. Therefore, a data driver is independently provided for every color, as shown in FIG. 8, thereby enabling control to be independently performed for each color.
However, the connection between the PDP and the data driver IC shown in FIG. 8 has a disadvantage that is makes interconnection from the data driver 31 to the PDP 21 complicated.
In general, the data driver 31 and the PDP 21 are connected by means of a flexible printed-circuit board (hereinafter, FPC) and the like. However, when the connection shown in FIG. 8 is formed in the FPC for connecting a printed-circuit board on which the data driver IC is mounted to the PDP, it is necessary to make the size of the printed-circuit board larger or to increase the number of layers in the printed-circuit board. Therefore, the cost inevitably increases.
Especially, it is recently common to use COF (Chip On Film), TCP (Tape Carrier Package), or the like in which the data driver IC is directly mounted on the FPC in a PDP in order to reduce the cost. In this case, the interconnection shown in FIG. 8 requires mounting of at least three data driver ICs on the FPC, thus increasing the size of the FPC. Therefore, the cost increases as compared with a case in which the data driver IC is mounted on the printed-circuit board.
Moreover, it is necessary to use a double-sided FPC in order to achieve the interconnection shown in FIG. 8. However, the use of the double-sided FPC is not possible from a practical viewpoint because the double-sided FPC further increases the cost. In addition, mounting of a plurality of data driver ICs each having a reduced number of output terminals on the FPC can be considered. In this case, however, the number of the used ICs increases, thus inevitably increasing the cost.